Minimum hardware serial PID regulator for high efficiency, low power digital DC-DC converters

This paper focuses on the minimum hardware implementation of a digital compensator for digitally controlled dc-dc converters. A novel serial PID architecture is presented that, together with the adopted representation of controller parameters, minimizes the area requirements while allowing the representation of a wide range of parameter values. Large multipliers and wide look-up tables are thus avoided, making this architecture well suited to applications where small size and low power consumption are required. Analysis of the serial PID compensator and simulation results are presented for a multi-mode buck converter for automotive applications, highlighting the advantages of the proposed architecture. ©2010 IEEE.