We present a broad set of experiments on silicon
nitride-based memories aimed at the investigation of the vertical
position of the charge trapped in the nitride layer of siliconoxide–
nitride–oxide-semiconductor (SONOS) memories during
program and erase in the tunneling regime. The results obtained
for SONOS devices with conventional oxide–nitride–oxide and
oxide–nitride–oxide–nitride–oxide gate stacks, as well as with
high-κ top dielectric, have been validated by comparing different
characterization techniques. It has been shown that, for SONOS
cells, the charge centroid is located in the center of the silicon
nitride layer, and its position is quite insensitive to the program
or erase conditions and to the gate-stack composition.
