In this work, the effect of digital CMOS technology
down scaling on the performances of MOS Current Mode Logic
frequency dividers is addressed. A fast and effective methodology
to design the dividers is presented. The insight given by the
methodology is then exploited to study the down scaling of
MCML dividers by considering two CMOS technologies representative
of the 130nm and 90nm technology nodes. The model
provides quantitatively accurate predictions of the advantages
of scaling on current consumption and maximum frequency of
operation.
