Runtime Verification is a lightweight technique that complements other
verification methods in an effort to ensure software correctness.
The technique poses novel questions to software engineers: it is not easy to
identify which specifications are amenable to runtime monitoring, nor is it
clear which monitors effect the required runtime analysis correctly.
This exposition targets a foundational understanding of these questions.
Particularly, it considers an expressive specification logic (a syntactic
variant of the mmucalc) that is agnostic of the verification method used,
together with an elemental framework providing an operational semantics for the
runtime analysis performed by monitors.
The correspondence between the property satisfactions in the logic on the one
hand, and the verdicts reached by the monitors performing the analysis on the
other, is a central theme of the study.
Such a correspondence underpins the concept of monitorability, used to identify
the subsets of the logic that can be adequately monitored for by RV.
Another theme of the study is that of understanding what should be expected of a
monitor in order for the verification process to be correct.
We show how the monitor framework considered can constitute a basis whereby
various notions of monitor correctness may be defined and investigated.
