Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm

In this paper, stack forcing and back biasing are analyzed as techniques to reduce leakage in active mode in FinFET VLSI circuits. Analysis is focused on buffers as representative circuit example, and is based on mixed-mode device-circuit simulations on 27-nm and 40-nm FinFET technologies. Voltage limits for back biasing are discussed. Results contradicting usual assumptions for bulk CMOS are found, and are explicitly justified by FinFET-specific features. Analysis shows that back biasing is very effective in reducing leakage with a quite limited speed penalty in sub- 45nm FinFET. On the other hand, stack forcing is rather ineffective and strongly degrades speed. Hence, BB is certainly the first option to consider in FinFET circuits, whereas stack forcing makes sense only if used jointly with BB when leakage has to be further reduced compared to pure BB.