The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) during programming, and the drain disturb current (DDC), defined as the hole gate current Igh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper Source/Drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively.
