Automating the Layout of Analog Circuits: A Machine Learning-Based Approach

Processes are nowadays permeated by the usage of artificial intelligence (AI) techniques, aiming at boosting their efficiency and accessibility. Such extensive adoption of AI methods has been fueled by remarkable progress in the chip manufacturing industry, particularly through the reduction in transistor sizes and circuit components in general. These advancements have made available an enormous amount of computational power, enabling to advance the status of AI-based solutions, especially in fields such as natural language processing. Leveraging AI to accelerate and optimize chip design has, in turn, emerged as a critical research direction. Significant improvements have been reached in the digital circuits domain, especially with the adoption of automated learning-based frameworks. On the contrary, the field of analog circuit design, especially for what concerns the layout phase, continues to lag behind its digital counterpart in terms of automation, as it is affected by unique challenges originated from specific electric and topological constraints to abide by. As a result, the proposed solutions to streamline the layout procedure have seen limited applicability at the industrial level. This thesis provides a wide range of techniques for generating the layout of analog integrated circuits, with a specific focus on leveraging reinforcement learning (RL) for floorplanning, along with pathfinding and deterministic approaches for efficient routing. We start with a dual development of a floorplanning engine, one combining RL and simulated annealing (SA) and another solely on RL mimicking the SA search process. An obstacle-avoiding rectilinear Steiner tree global routing system is also proposed and integrated with the floorplanning engine into an existing procedural layout generation framework for finalizing layouts. We demonstrate the effectiveness of learning-based approaches in exploring a large solution space better than metaheuristic techniques, while also reducing runtimes compared to manually crafted layouts. Then, to improve generalization and transferability, we devise a novel floorplanning solution that combines relational graph convolutional neural networks (R-GCNs) with RL to scale layout generation to more complex circuits. Devices are placed on a discretized grid, providing greater flexibility for the RL agent to optimize circuit area and proxy wirelength metrics. Moreover, we propose a plug-and-play integration based on a beam search strategy to enhance the RL inference process, allowing for flexible objective weighting tailored to specific use cases and addressing congestion without policy finetuning. Lastly, we present a routing-aware version of the floorplanning engine, which builds upon the R-GCN RL approach. This enhanced framework leverages a novel U-Net policy, dynamic routing resource estimation, and revised reward scheme for delivering routing-ready floorplans. A prototype A* rip-up and reroute analog routing engine is also proposed, allowing the generation of complete layouts, showing how this novel framework consistently outperforms previous methods in both routability and placement performance.

Processes are nowadays permeated by the usage of artificial intelligence (AI) techniques, aiming at boosting their efficiency and accessibility. Such extensive adoption of AI methods has been fueled by remarkable progress in the chip manufacturing industry, particularly through the reduction in transistor sizes and circuit components in general. These advancements have made available an enormous amount of computational power, enabling to advance the status of AI-based solutions, especially in fields such as natural language processing. Leveraging AI to accelerate and optimize chip design has, in turn, emerged as a critical research direction. Significant improvements have been reached in the digital circuits domain, especially with the adoption of automated learning-based frameworks. On the contrary, the field of analog circuit design, especially for what concerns the layout phase, continues to lag behind its digital counterpart in terms of automation, as it is affected by unique challenges originated from specific electric and topological constraints to abide by. As a result, the proposed solutions to streamline the layout procedure have seen limited applicability at the industrial level. This thesis provides a wide range of techniques for generating the layout of analog integrated circuits, with a specific focus on leveraging reinforcement learning (RL) for floorplanning, along with pathfinding and deterministic approaches for efficient routing. We start with a dual development of a floorplanning engine, one combining RL and simulated annealing (SA) and another solely on RL mimicking the SA search process. An obstacle-avoiding rectilinear Steiner tree global routing system is also proposed and integrated with the floorplanning engine into an existing procedural layout generation framework for finalizing layouts. We demonstrate the effectiveness of learning-based approaches in exploring a large solution space better than metaheuristic techniques, while also reducing runtimes compared to manually crafted layouts. Then, to improve generalization and transferability, we devise a novel floorplanning solution that combines relational graph convolutional neural networks (R-GCNs) with RL to scale layout generation to more complex circuits. Devices are placed on a discretized grid, providing greater flexibility for the RL agent to optimize circuit area and proxy wirelength metrics. Moreover, we propose a plug-and-play integration based on a beam search strategy to enhance the RL inference process, allowing for flexible objective weighting tailored to specific use cases and addressing congestion without policy finetuning. Lastly, we present a routing-aware version of the floorplanning engine, which builds upon the R-GCN RL approach. This enhanced framework leverages a novel U-Net policy, dynamic routing resource estimation, and revised reward scheme for delivering routing-ready floorplans. A prototype A* rip-up and reroute analog routing engine is also proposed, allowing the generation of complete layouts, showing how this novel framework consistently outperforms previous methods in both routability and placement performance.