We present the first computational study employing a full
quantum transport model to investigate the effect of interface
traps in nanowire InAs Tunnel FETs and MOSFETs. To this
purpose, we introduced a description of interface traps in a
simulator based on the NEGF formalism and on a 8×8 k·p
Hamiltonian and accounting for phonon scattering. Our results
show that: (a) even a single trap can detereorate the inverse
sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b)
the inelastic phonon assisted tunneling (PAT) through interface
traps results in a temperature dependence of the Tunnel FETs
IV characteristics; (c) the impact of interface traps on Iof f is
larger in Tunnel FETs than in MOSFETs; (d) interface traps
represent a sizable source of device variability.
