In this paper the modelling approaches for determination of the drain current in nanoscale MOSFETs pursued by various partners in the frame of the European Projects Pullnano and Nanosil are mutually compared in terms of drain current and internal quantities (average velocity and inversion charge). The comparison has been carried out by simulating template devices representative of 22 nm Double-Gate and 32 nm Single-Gate FD-SOI. A large variety of simulation models has been considered, ranging from drift-diffusion to direct solutions of the Boltzmann-Transport-Equation. The predictions of the different approaches for the 32 nm device are quite similar. Simulations of the 22 nm device instead, are much less consistent. Comparison with experimental data for a 32 nm device shows that the modeling approach used to explain the mobility reduction induced by the high-k dielectric is critical.
