Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs - Part I: Model Description and Single Trap Analysis in Tunnel-FETs

This paper and the companion work present a full quantum study of the influence of interface traps on the I–V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green’s function formalism, employing an 8×8 k·p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I–V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I–V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I–V characteristics.