Conventional materials and device geometries have reached a limit that prevents further scaling. III-V compound materials have been proposed as a possible replacement of Silicon. Electrons moving inside these materials have a higher velocity, which allows higher currents at lower supply voltages, which reduces the dynamic power consumption. These materials, however, pose additional modelling challenges when one tries to use TCAD software to guide the design and fabrication of advanced nanoscale devices. Models for these devices are complicated and heavy from the computational point of view. Also, since these materials do not have a native dielectric like SiO2 and due to higher degeneracy, trap states located at the interface between the semiconductor and the dielectric play a much greater role that in Si-SiO2 interfaces. This work has two purposes: the first is to reduce the computational burden of the models for these materials via TCAD code optimisation and parallelisation; the second is the implementation of a model that allows to assess the impact of interface traps on the performance of the device.
