In this paper, a novel technique to reduce the
leakage current under an assigned delay constraint is
presented for FinFET forced stacks. This technique is based
on the adoption of different back bias voltages in stacked fourterminal
(4T) FinFETs (as is well known, this would not be
possible in bulk CMOS circuits). In particular, a Reverse
Back Bias (RBB) voltage is applied to one of the two stacked
transistors to reduce its leakage at the cost of a delay penalty,
whereas a Forward Back Bias (FBB) voltage is applied to the
other one to compensate this delay degradation. Mixed devicecircuit
simulations for 40-nm FinFETs show that the proposed
“mixed FBB/RBB” technique permits a leakage reduction by
one order of magnitude or more as compared with traditional
transistor stacks at same delay.
