Latch-up in CMOS circuits: a review

In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch-up, represents one of the most serious limitations for further dimension scaling in the deep sub-micron range. For this reason latch-up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.