We present an improved methodology to calibrate nominal SPICE models to individual or average PCM measurements at the die, wafer or lot level. The method overcomes previous difficulties in the structured handling of huge amounts of PCM data and it is validated in a state-of-the-art mixed-signal system-on-chip product development environment for the 65 nm CMOS technology node. The proposed approach is especially useful for real time process control to tackle model-hardware correlation problems in a multi-foundry design environment, to ease the burden of transferring designs to new production sites and to complement common tools available to the designers to cope with process variability such as worst-case corner models and Monte Carlo simulations.
