An improved procedure to test CMOS ICs for Latch-up

An improved, more complete strategy for latch-up testing of CMOS ICs is proposed in order to take into account important effects that have been neglected by standard procedures, but which are shown to reduce considerably the circuit resistance to latch-up. These phenomena include interactions among carriers injected by different p-n-p-n structures, voltage drops on power supply and ground lines caused by output pin load currents, and effects of power supply voltage and chip heating. All experiments with regard to this work have been performed by means of automatic test equipment, which provides the possibility of completely controlling the circuit state and operating conditions during testing