In this paper we applied the statistical model for independent
defects described in Part I, to experimental data measured
on Flash memory arrays. The model, developed to describe
the stress-induced leakage current (SILC) statistics, allowed us to
study the oxide trap generation during program/erase (P/E) stress
and to extract the discrete probability distribution (DPD) of the
gate current increase due to the single oxide defect. For all the analyzed
nonvolatile memory arrays and for all the P/E stresses, the
experimental results are consistent with the simulations carried out
in Part I, thus confirming the reliability of the statistical model and
of its validation procedure. Measurements on Flash cell arrays with
different oxide thickness show that the number of generated oxide
traps increases linearly with the number of P/E cycles in the early
stage of the stress. It is shown, for the first time, that the extracted
DPD of the single-trap exhibits long tails with power law dependence
on the trap current and with a slope of the tail that decreases
with decreasing oxide thickness. These tails are responsible for the
cells with the largest SILC values in the Flash memory arrays.
