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Hysteresis cycle in the Latch-up characteristic of wide CMOS structures

SELMI, Luca
•
SANGIORGI, Enrico
•
CRISENZA G
altro
RICCO B.
1988
  • journal article

Periodico
IEEE ELECTRON DEVICE LETTERS
Abstract
Experimental results are interpreted in terms of a simple lumped-element model that is also used to reproduce the hysteresis phenomenon with discrete components. The hysteresis is related to a three-dimensional (3-D) nonuniformity in the current distribution. Such hysteresis can lead to an erroneous evaluation of latchup parameters, such as the holding current density.
DOI
10.1109/55.694
WOS
WOS:A1988N116800007
Archivio
http://hdl.handle.net/11390/681895
info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-0024012253
Diritti
closed access
Web of Science© citazioni
3
Data di acquisizione
Mar 17, 2024
Visualizzazioni
1
Data di acquisizione
Apr 19, 2024
Vedi dettagli
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