The Large Hadron Collider (LHC) running at
CERN will soon be upgraded to increase its luminosity giving rise
to radiations reaching the level of GigaRad Total Ionizing Dose
(TID). This paper investigates the impact of such high radiation
on transistors fabricated in a commercial 28 nm bulk CMOS
process with the perspective of using it for the future siliconbased
detectors. The DC electrical behavior of nMOSFETs is
studied up to 1 Grad TID. All tested devices demonstrate to
withstand that dose without any radiation-hard layout techniques.
In spite of that, they experience a significant drain leakage
current increase which may affect normal device operation. In
addition, a moderate threshold voltage shift and subthreshold
slope degradation is observed. These phenomena have been linked
to radiation-induced effects like interface and switching oxide
traps, together with parasitic side-wall transistors.
