We present gate all around strained Si (sSi) nanowire array
TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V
measurements provide small SS and record I60 of
1×10-2μA/μm at 300K due to the suppression of trap assisted
tunneling (TAT). Scaling the nanowires to 10 nm diameter
greatly suppresses the impact of TAT and improves SS and
ION. Transient analysis of complementary TFET inverters
demonstrates experimentally for the first time that device
scaling and improved electrostatics yields to faster time
response.
