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Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks

Baccarin D
•
Alioto M.
•
ESSENI, David
2012
  • journal article

Periodico
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Abstract
In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a reverse back bias voltage is applied to one of the two stacked transistors to reduce its leakage at the cost of a delay penalty, whereas a forward back bias voltage is applied to the other one to compensate this delay degradation. The technique is assessed by means of mixed device-circuit simulations for FinFETs that are representative of 40- and 27-nm technology generations. Results show that a leakage reduction by up to 50 can be achieved as compared with traditional transistor stacks, while keeping same speed, dynamic energy, and sensitivity to process/voltage/temperature variations.
DOI
10.1109/TVLSI.2011.2158614
WOS
WOS:000305605800011
Archivio
http://hdl.handle.net/11390/868316
info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-84862666522
Diritti
closed access
Scopus© citazioni
15
Data di acquisizione
Jun 2, 2022
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Web of Science© citazioni
16
Data di acquisizione
Mar 27, 2024
Visualizzazioni
1
Data di acquisizione
Apr 19, 2024
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