115[1] picture
 
 
Ruolo
Docenti di ruolo di Ia fascia
Qualifica (ricerca)
Professori Ordinari
 
Area Ministeriale
AREA MIN. 09 - Ingegneria industriale e dell'informazione
Macro-settore concorsuale
09/D - INGEGNERIA CHIMICA E DEI MATERIALI
Academic SSD
Settore ING-IND/24 - Principi di Ingegneria Chimica
Short CV

Maurizio Fermeglia is full professor at the Department of Engineering and Architecture of the University of Trieste, where he holds the course in Chemical and Biochemical Reaction Engineering and Process and Product design. From 2006 to 2012 he was the head of the Department of Industrial Engineering & Information Technology, from 2010 to 2012 he served as president of the Research board of the University of Trieste. He was the director of the Ph.D. School of Nanotechnology at the University of Trieste from 2007 to 2013. From 2013 to 2019, he was the Rector of the University of Trieste.

Professor Maurizio Fermeglia graduated in Chemical Engineering at the Engineering Faculty of the University of Trieste in 1980. He got his habilitation for chemical engineer in 1985. Professor Fermeglia spent the period 1981 - 83 as researcher at the Denmark Technical University (DTH). In 1984, he joined the department of chemical engineering at the University of Trieste as Researcher. His current position is full professor at the Department of Engineering & Architecture of the University of Trieste, where he holds the course in ‘Chemical and Biochemical Reaction Engineering’’ and ‘Data base design’. He has been the head of the Department of Industrial Engineering & Information Technology from 2006 to 2012 and the president of the Research board of the University of Trieste from 2010 to 2012. He was the director of the Ph.D. School of Nanotechnology at the University of Trieste from 2007 to 2013. From 2013 to 2019, he was the Rector of the University of Trieste.

Loading... 6 0 20 0 false
Loading... 5 0 20 0 false
Loading... 8 0 20 0 false
Loading... 10 0 20 0 false
Loading... 9 0 20 0 false
Loading... 7 0 20 0 false
Loading... 12 0 20 0 false
Loading... 11 0 20 0 false